As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in various electronic devices. Generally, a solid state storage device comprises a non-volatile memory. After data are written to the non-volatile memory, if no electric power is supplied to the solid state storage device, the data are still retained in the non-volatile memory.
U.S. Pat. No. 9,922,706 discloses a solid state storage device using a state prediction method. The state prediction method uses a prediction function to predict the state of the solid state storage device in the future time, predict the suitable decoding process or provide the suitable read voltage.
FIG. 1 is a schematic functional block diagram illustrating the architecture of a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 is connected with a host 14 through an external bus 12. For example, the external bus 12 is a USB bus, a SATA bus, a PCIe bus, a M.2 bus, a U.2 bus, or the like.
The solid state storage device 10 comprises a control circuit 101 and a non-volatile memory 105. The control circuit 101 is connected with the non-volatile memory 105 through an internal bus 107. According to a command from the host 14, the control circuit 101 stores the received write data into the non-volatile memory 105, or the control circuit 101 acquires a read data from the non-volatile memory 105 and transmits the read data to the host 14.
The control circuit 101 further comprises an error correction code (ECC) circuit 104 and a function storage circuit 106. The ECC unit 104 is used for correcting the error bits of the read data. After the error bits of the read data are corrected, accurate read data are transmitted to the host 14. Moreover, plural prediction functions are stored in the function storage circuit 106.
After the solid state storage device 10 leaves the factory, if the solid state storage device 10 has been programmed and erased many times, the threshold voltage distribution curves of the storing state of the memory cells in the non-volatile memory 105 are possibly shifted. Under this circumstance, a read failure problem occurs.
When the non-volatile memory 105 is in a failure mode, the read failure problem occurs. For example, the failure mode includes a cycling mode, a high/room temperature baking mode, a read disturb mode, a cross-temperature read/write mode, a program disturb mode, a data retention mode, and the like. In the failure mode, the control circuit 101 cannot accurately acquire the read data. Then, the control circuit 101 performs a read retry process.
FIG. 2 schematically illustrates a flowchart of a read retry method for the conventional solid state storage device. During the read cycle, the control circuit 101 performs a decoding process A. In the decoding process A, a hard decoding operation is performed according to a default voltage set. That is, the control circuit 101 provides the default voltage set to the non-volatile memory 105, and the ECC circuit 104 performs the hard decoding operation to correct the read data.
If the error bits of the read data can be corrected, it means that the decoding process A passes and the decoding operation is successfully done. Consequently, the accurate read data is transmitted from the control circuit 101 to the host 14. Whereas, if the error bits of the read data cannot be corrected, the read data is not accurately acquired and the decoding process A fails. Then, the control circuit 101 performs the read retry process.
After the control circuit 101 enters the read retry process, a decoding process B is firstly performed. In the decoding process B, a hard decoding operation is performed according to a retry voltage set. For example, the control circuit 101 provides one of plural retry voltage sets to the non-volatile memory 105 to acquire the read data. Then, the ECC circuit 104 performs the hard decoding operation to correct the read data. If the error bits of the read data can be corrected, it means that the decoding operation is successfully done to pass the decoding process B. Consequently, the accurate read data is transmitted from the control circuit 101 to the host 14. Whereas, if the error bits of the read data cannot be corrected, the read data is not accurately acquired and the decoding process B fails. Then, the control circuit 101 continuously provides another one of the plural retry voltage sets to the non-volatile memory 105 and performs the decoding process B.
If the decoding operation is successfully done according to one of the plural retry voltage sets, it means that the decoding process B passes. Whereas, if the data cannot be successfully decoded according to the entire of the retry voltage sets, it means that the decoding process B fails. Then, the control circuit 101 performs a decoding process C. Obviously, the time period of performing the decoding process B is longer than the time period of performing the decoding process A.
In the decoding process C, a soft decoding operation is performed according to the retry voltage sets. Generally, the soft decoding operation has better error correction capability than the hard decoding operation. However, the time period of performing the soft decoding operation is longer. That is, the time period of performing the decoding process C is longer than the time period of performing the decoding process B.
Similarly, if the decoding operation is successfully done by the control circuit 101 according to one of the plural retry voltage sets, it means that the decoding process C passes. Consequently, the accurate read data is transmitted from the control circuit 101 to the host 14. Whereas, if the data cannot be successfully decoded according to the entire of the retry voltage sets, it means that the decoding process C fails. Under this circumstance, the control circuit 101 confirms that the read data cannot be accurately acquired, and the control circuit 101 generates a failed message to the host 14 to indicate that the decoding process fails.
As mentioned above, if the solid state storage device 10 is in the failure mode, the decoding process A fails and the control circuit 101 enters the read retry process. In the read retry process, the control circuit 101 has to perform the decoding process B at first. If the control circuit 101 confirms that the decoding process B fails, the control circuit 101 performs the decoding process C. If the control circuit 101 confirms that the decoding process C fails, the control circuit 101 issues the failed message to the host 14 and is unable to provide the accurate read data.
If the time period of performing the read retry process is very long, the read speed of the solid state storage device 10 is largely decreased. To solve the problem mentioned above, the manufacturer of the solid state storage device 10 collects plural state parameters of all blocks in the non-volatile memory 105 before the solid state storage device 10 leaves the factory. Moreover, the state parameters are contained in an information table of the non-volatile memory 105 as a database.
FIG. 3 illustrates an information table of the non-volatile memory according to the prior art. In FIG. 3, the state parameters contain the program time (Pt), the erase time (Et), the error bit number (Eb), the real-time read voltage shift (Vrb) and the real-time decoding process (Dp).
For example, the state parameters of the first block (Block_1) indicates that the program time is 1894 μs, the erase time is 5615 μs, the error bit number is 55, the real-time read voltage shift Vrb is −3 and the decoding process A is the suitable decoding process. If the read voltage shift Vrb is −3, the real-time read voltage shift Vrb is 3 voltage units smaller than the default read voltage. The voltage unit is defined by the manufacture of the non-volatile memory. If the voltage unit is 10 mV, Vrb is −3 indicates that the real-time read voltage shift Vrb is 30 mV smaller than the default read voltage.
After the information table is established, the manufacturer of the solid state storage device 10 acquires plural prediction functions and stores the prediction functions in the function storage circuit 106. After the state parameters corresponding to a specified block are inputted into the prediction function, the state of the specified block in a future time (e.g., after 2 months) is predicted. For example, the read voltage shift condition after 2 months or the suitable decoding process after 2 months is predicted.
For example, after the state parameters of the specified block are substituted into the future decoding process prediction function, the control circuit 101 may predict that the decoding process B or the decoding process C will be the suitable decoding process in 2 months. Under this circumstance, the control circuit 101 tags the specified block. When the host 14 intends to read the data from the specified block, the control circuit 101 acquires the read data according to the predicted decoding process (i.e., the decoding process B or the decoding process C).
Alternatively, the control circuit 101 may predict that the decoding process for the specified block will fail in 2 months. For preventing the read failure condition, the control circuit 101 can previously store the data of the specified block in another block of the non-volatile memory 105. Since the time period of performing the read retry process is reduced, the read speed of the solid state storage device 10 is increased.
However, the prediction result of the prediction function is not always accurate. If the control circuit 101 predicts that the condition of the specified block will be good in 2 months after the plural state parameters are inputted into the prediction function, the decoding process A passes and the decoding operation is successfully done. Under this circumstance, the control circuit 101 does not perform any operation to the data of the specified block.
If the host 14 continuously reads the data of the specified block, the specified block is possibly suffered from the read disturb failure mode in the short time period. Consequently, the data of the specified block will not be successfully decoded by decoding process A in 2 months. Meanwhile, it is necessary to perform the decoding process B or the decoding process C for successfully decoding the data or, what is worse, the decoding processes B and C are failed. Since the prediction result is erroneous, the read speed of the solid state storage device 10 is decreased or the data is unable to be accurately read.